1. Technical Field
The present invention relates to memory devices and, more particularly, to nonvolatile memory devices and methods of manufacturing the same.
2. Discussion of the Related Art
Nonvolatile memory devices retain their stored data even when their power supplies are turned off. Electrically erasable and programmable read only memory (EEPROM) devices are a form of nonvolatile memory devices which may be electrically programmed and erased. The EEPROM devices may comprise a floating gate tunnel oxide (FLOTOX) type EEPROM device, and the FLOTOX type EEPROM device may comprise a plurality of memory cells.
A unit cell of the FLOTOX type EEPROM device may include a memory transistor for storing a single bit data and a selection transistor for controlling an electrical access to the memory transistor. The memory transistor may be laterally spaced apart from the selection transistor on a semiconductor substrate. The memory transistor may include a floating gate which is electrically insulated from other conductive elements adjacent thereto. The memory transistor may further include a tunnel oxide layer disposed between a portion of the floating gate and the semiconductor substrate as well as a memory gate oxide layer which extends from the tunnel oxide layer along a surface of the semiconductor substrate. The tunnel oxide layer may be thinner than the memory gate oxide layer. The memory transistor may further include an inter-gate dielectric layer on the floating gate and a control gate on the inter-gate dielectric layer. The memory gate oxide layer, the tunnel oxide layer, the floating gate, the inter-gate dielectric layer, and the control gate may constitute a stacked gate structure. The memory transistor may also include a source region and a floating junction region formed in the semiconductor substrate. The source region and the floating junction region may be disposed at opposite sides of the stacked gate structure.
When a program voltage or an erasure voltage is applied between the control gate and the floating junction region, a Fowler-Nordheim (F-N) tunneling current may flow through the tunnel oxide layer. As a result, electrons in the semiconductor substrate may be injected into the floating gate, or electrons in the floating gate may be injected into the semiconductor substrate. When the electrons in the semiconductor substrate are injected into the floating gate, the memory transistor may be programmed. When the electrons in the floating gate are injected into the semiconductor substrate, the memory transistor may be erased.
The program voltage or the erasure voltage may be determined according to a coupling ratio of the memory transistor. The coupling ratio may depend upon the ratio of a voltage induced at the floating gate to a voltage applied to the control gate. That is, the coupling ratio may be approximately equal to the ratio of an inter-gate dielectric capacitance between the control gate and the floating gate to a total capacitance of the inter-gate dielectric capacitance and a tunnel oxide capacitance between the floating gate and the semiconductor substrate. Thus, when the coupling ratio is close to “1,” the program efficiency and the erasure efficiency may increase to reduce the program voltage and the erasure voltage.
The inter-gate dielectric capacitance may be increased to increase the coupling ratio. An overlap area between the control gate and the floating gate may be increased and/or a thickness of the inter-gate dielectric layer may be reduced to increase program efficiency and erasure efficiency. In particular, as the nonvolatile memory devices including the EEPROM device become more highly integrated, there may be a need to reduce the thickness of the inter-gate dielectric layer to scale down the memory device. However, there may be a limitation in reducing the thickness of the inter-gate dielectric layer. This is because a leakage current flowing through the inter-gate dielectric layer may be increased and may thus cause degradation of the program efficiency and the erasure efficiency when the thickness of the inter-gate dielectric layer is decreased. Accordingly, the area of the inter-gate dielectric layer between the control gate and the floating gate may be increased in order to realize high performance nonvolatile memory devices with a high integration density.